FPGA软件工程师,激光部 1-2k
深圳-宝安区 5年以上 统招本科 招1人 9月23日更新
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职位介绍
Gerneral Purpose 1、Familiar with FPGA general-purpose logic design and capable of independently developing basic modules such as state machines, FIFOs, RAMs, CDCs, multi-clock domains, data buffers, and interface controls. 2、Familiar with the development of FPGA modules related to laser control, including flip-flops, timing control, pulse generators, DDS, ADC/DAC control, GPIO, safety interlocks, and fault protection. Responsibilities: 1. Responsible for the design, development, and maintenance of FPGA solutions for laser control systems to implement product functionality; 2. Responsible for FPGA logic design, Verilog/VHDL code development, simulation verification, timing analysis, and optimization; 3. Responsible for the development of digital signal processing modules such as high-speed ADCs, DACs, and DDSs to enable real-time control of laser power, pulse width, frequency, and other parameters; 4. Responsible for implementing laser control algorithms on the FPGA, including but not limited to: · Pulse Generator · Timing Control · Trigger Management · PWM Control · DDS Waveform Generation · PID Control · SOA Protection · Low Frequency Compensation · Real-time Power Feedback Control 5. Responsible for high-speed data acquisition (DAQ) and data processing to implement functions such as PD sampling, energy monitoring, temperature monitoring, and current monitoring; 6. Responsible for developing control logic for various laser functional modules, including: · Seed Laser · Pre-Amp · Power Amp · AOM Driver · TEC Control · Pump Driver · Shutter · Interlock · Simmer · Safety Protection 7. Responsible for data exchange and system integration between the FPGA, ARM, DSP, and MCU, and for completing hardware and software co-debugging; 8. Responsible for developing various communication interfaces, including UART, SPI, I²C, CAN, Ethernet, LVDS, AXI, etc.; 9. Responsible for system debugging, issue troubleshooting, resource optimization, and timing convergence to improve system stability and reliability; 10. Prepare design, development, test, and maintenance documentation. Requirements 1、Bachelor or above degree 2、 Knowledge/skills : -Proficient in Verilog HDL (or VHDL) development; -.Proficient in using development tools such as Vivado and Quartus Prime; -Familiar with the FPGA development process, including: n RTL Design n Functional Simulation n Timing Simulation n Synthesis n Place & Route 3、CET 4 薪资面议
其他信息
语言要求:英语
行业要求:全部行业

公司简介

通快集团成立于1923年,作为工业4.0创始成员及德国技术与创新领域*高荣誉2020年”德国未来奖”获得者,历经百年发展成长为机床、激光和电子领域的市场及技术***,为汽车、新能源、半导体、医疗器械、航空航天等领域提供智能设备及解决方案。落户于德企之乡太仓的通快中国,在20余年的蓬勃发展中,现已拥有超过1000名员工,在27个省市拥有服务和销售办事处。信任勇敢的想法代表着通快开放的空间和独立的思维。
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更新时间:2026-09-24