资深芯片后端设计工程师

Responsibilities:
Execute the whole Physical Design flow includeFloorplan/Placement/CTS/Routing/Physical Verification
Work with front end design Engineers to achieve timingclosure for both partition level and full chip level
IO ring design
Cross talk Analysis
IR Drop and Power Integrity Analysis
Execute ECO's
Develop and enhance entire physical design flow at bothchip and block level
Requirements:
BS/MS in Electrical or Computer Engineering with 5+ yearsexperience in physical design
Experience with advanced process, experience with hierarchicaldesign flow
Hands-on experience in full-chip/sub-chip Static TimingAnalysis. CPU related timing convergence background would be a plus
Hands on experience in logic synthesis and equivalencechecking/FV required
Expertise in physical design and optimization e.g.placement, routing, cell sizing, buffering, logic restructuring, etc. toimprove timing and power required. Background in implementing them through ECOsrequired
Understanding of DFT logic and hands-on experience in designclosure taking into account DFT logic required. DFT timing closure for variousmodes e.g. scan shift and capture, transition faults, BIST, etc. would be aplus
Expertise in analyzing and converging crosstalk delay,noise glitch, and electrical/manufacturing rules in deep-sub micron processes
Understand process variation effect modeling andexperience in design convergence taking into account variations required
Experience in critical path planning and crafting.Experience in circuits, SPICE simulations, and/or transistor level STA would bea plus
Expertise and in-depth knowledge of industry standard EDAtools required
Proficiency in scripting languages, such as, Perl, Tcl,Make, etc. Experience in methodology and/or flow automation would be a plus